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1 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram mt4c1m16c3, mt4lc1m16c3 for the latest data sheet revisions, please refer to the micron web site: www.micron.com/datasheets fpm dram pin assignment (top view) features ? jedec- and industry-standard x16 timing, functions, pinouts, and packages high-performance, low-power cmos silicon-gate process single power supply (+3.3v 0.3v or 5v 0.5v) all inputs, outputs and clocks are ttl-compatible refresh modes: ras#-only, cas#-before-ras# (cbr) and hidden optional self refresh (s) for low-power data retention byte write and byte read access cycles 1,024-cycle refresh (10 row, 10 column addresses) fast-page-mode (fpm) access options marking voltage 1 3.3v lc 5v c packages plastic soj (400 mil) dj plastic tsop (400 mil) tg timing 50ns access -5 60ns access -6 refresh rates standard refresh (16ms period) none self refresh (128ms period) s 2 ? operating temperature range commercial (0 o c to +70 o c) none extended (-20 o c to +80 o c) et 3 part number example: mt4lc1m16c3dj-5 note : 1. the third field distinguishes the low voltage offering: lc designates v cc = 3.3v and c designates v cc = 5v. 2. contact factory for availability. 3. available only on mt4c1m16c3 (5v) 1 meg x 16 fpm dram part numbers part number supply package refresh mt4lc1m16c3dj-6 3.3v soj standard mt4lc1m16c3dj-6 s 3.3v soj self mt4lc1m16c3tg-6 3.3v tsop standard mt4lc1m16c3tg-6 s 3.3v tsop self mt4c1m16c3dj-6 5v soj standard mt4c1m16c3tg-6 5v tsop standard general description the 1 meg x 16 dram is a randomly accessed, solid- state memory containing 16,777,216 bits organized in a x16 configuration. the 1 meg x 16 dram has both byte write and word write access cycles via two cas# pins (casl# and cash#). these function identi- cally to a single cas# on other drams in that either casl# or cash# will generate an internal cas#. the cas# function and timing are determined by the first cas# (casl# or cash#) to transition low and 44/50-pin tsop v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc nc nc we# ras# nc nc a0 a1 a2 a3 v cc 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc nc casl# cash# oe# a9 a8 a7 a6 a5 a4 v ss 42-pin soj v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc nc we# ras# nc nc a0 a1 a2 a3 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc casl# cash# oe# a9 a8 a7 a6 a5 a4 v ss note: the # symbol indicates signal is active low. key timing parameters speed t rc t rac t pc t aa t cac t rp -5 84ns 50ns 20ns 25ns 15ns 30ns -6 110ns 60ns 35ns 30ns 15ns 40ns
2 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram the last cas# to transition back high. use of only one of the two results in a byte access cycle. casl# transitioning low selects an access cycle for the lower byte (dq0-dq7), and cash# transitioning low se- lects an access cycle for the upper byte (dq8-dq15). each bit is uniquely addressed through the 20 ad- dress bits during read or write cycles. these are entered ten bits (a0-a9) at a time. ras# is used to latch the first ten bits and cas# the latter ten bits. the cas# function is determined by the first cas# (casl# or cash#) to transition low and the last one to transition back high. the cas# function also determines whether the cycle will be a refresh cycle (ras#-only) or an active cycle (read, write, or read-write) once ras# goes low. the casl# and cash# inputs internally generate a cas# signal that functions identically to a single cas# input on other drams. the key difference is that each cas# input (casl# and cash#) controls its corre- general description (continued) sponding dq tristate logic (in conjunction with oe# and we#). casl# controls dq0-dq7 and cash# con- trols dq8-dq15. the two cas# controls give the 1 meg x 16 dram byte write cycle capabilities. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas, whichever occurs last. taking we# low will initiate a write cycle, selecting dq0-dq15. if we# goes low prior to cas# going low, the output pin(s) remain open (high-z) until the next cas# cycle. if we# goes low after cas# goes low and data reaches the output pins, data-out (q) is activated and retains the selected cell data as long as cas# and oe# remain low (regardless of we# or ras#). this late we# pulse re- sults in a read-write cycle. the 16 data inputs and 16 data outputs are routed through 16 pins using common i/o. pin direction is controlled by oe# and we#. casl# cas# ras# 10 10 no. 2 clock generator refresh controller no. 1 clock generator 1,024 x 1,024 x 16 memory array v dd v ss 10 oe# dq0 dq15 refresh counter cash# a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 1,024 1,024 x 16 16 10 10 sense amplifiers i/o gating 1,024 data-out buffer we# 16 row- address buffers (10) row decoder column- address buffer data-in buffer column decoder 16 functional block diagram
3 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram general description (continued ) the mt4lc1m16c3 must be refreshed periodically in order to retain stored data. fast page mode access fast-page-mode operations allow faster data op- erations (read, write or read-modify-write) within a row-address-defined (a0-a9) page boundary. the fast-page-mode cycle is always initiated with a row address strobed in by ras#, followed by a column address strobed in by cas#. additional columns may be accessed by providing valid column addresses, strobing cas# and holding ras# low, thus executing faster memory cycles. returning ras# high termi- nates the fast-page-mode operation. returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standbylevel. the chip is also preconditioned for the next cycle during the ras# high time. memory cell data is retained in its correct state by maintaining power and executing anyras# cycle (read, write) or ras# refresh cycle (ras# only, cbr or hidden) so that all 1,024 combinations of ras# addresses (a0-a9) are executed at least every 16ms (128ms on the ?s? ver- sion), regardless of sequence. the cbr refresh cycle will also invoke the refresh counter and controller for row-address control. byte access cycle the byte writes and byte reads are determined by the use of casl# and cash#. enabling casl# will select a lower byte access (dq0-dq7), while enabling cash# will select an upper byte access (dq0-dq15). enabling both casl# and cash# selects a word write cycle. the 1 meg x 16 dram may be viewed as two 1 meg x 8 drams that have common input controls, with the exception of the cas# inputs. figure 1 illustrates the byte write and word write cycles. figure 2 illus- trates byte read and word read cycles. figure 1 word and byte write example stored data 1 1 0 1 1 1 1 1 ras# casl# we# x = not effective (don't care) address 1 address 0 0 1 0 1 0 0 0 0 word write lower byte write cash# input data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x input data 1 1 0 1 1 1 1 1 input data stored data 1 1 0 1 1 1 1 1 input data stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x 1 0 1 0 1 1 1 1 upper byte (dq8-dq15) of word lower byte (dq0-dq7) of word
4 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram stored data 1 1 0 1 1 1 1 1 ras# casl# we# z = high-z address 1 address 0 0 1 0 1 0 0 0 0 word read lower byte read stored data 1 1 0 1 1 1 1 1 cash# output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 upper byte (dq8-dq15) of word lower byte (dq0-dq7) of word 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 additionally, both bytes must always be of the same mode of operation if both bytes are active. a cas# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. for ex- ample, an early write on one byte and a late write on the other byte are not allowed during the same cycle. however, an early write on one byte and a late write on the other byte, after a cas# precharge has been satisfied, are permissible. dram refresh preserve correct memory cell data by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr or hidden) so that all 1,024 combinations of ras# addresses are executed within t ref (max), regardless of sequence. the cbr and extended and self refresh cycles will invoke the internal refresh counter for automatic ras# addressing. an optional self refresh mode is available on the ?s? version. the self refresh feature is initiated by per- forming a cbr refresh cycle and holding ras# low for the specified t rass. the ?s? option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended re- fresh period of 128ms, or 125s per row, when using a distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low- to-high transition. if the dram controller uses a dis- tributed cbr refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram controller utilizes a ras#-only or burst cbr refresh sequence, all 1,024 rows must be refreshed us- ing a minimum t rc refresh rate prior to resuming nor- mal operation. standby returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. the chip is preconditioned for the next cycle during the ras# high time. figure 2 word and byte read example
5 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram dc electrical characteristics and operating conditions (notes: 1, 5, 6; notes can be found on page 9); v cc (min) v cc v cc (max) 3.3v 5v parameter/condition symbol min max min max units notes supply voltage v cc 3 3.6 4.5 5.5 v input high voltage: valid logic 1; all inputs, i/os and any nc v ih 2 5.5 2.4 v cc + 1 v input low voltage: valid logic 0; all inputs, i/os and any nc v il -1.0 0.8 -0.5 0.8 v input leakage current: any input at v in (0v v in v cc + 0.3v) ; i i -2 2 -2 2 a all other pins not under test = 0v output high voltage: i out = -2ma v oh 2.4 ? 2.4 ? v output low voltage: i out = 2ma v ol ? 0.4 ? 0.4 v output leakage current: any output at v out [0v v out v cc (max)]; i oz -5 5 -5 5 a dq is disabled and in high-z state absolute maximum ratings* voltage on v cc pin relative to v ss 3.3v ..................................................... -1v to +4.6v 5v ........................................................... -1v to +7v voltage on nc, inputs or i/o pins relative to v ss 3.3v ..................................................... -1v to +5.5v 5v ........................................................... -1v to +7v operating temperature t a (commercial) ...................................... 0c to +70c t a (extended "et") ............................ -20c to +80c storage temperature (plastic) ............ -55c to +150c power dissipation ........................................................ 1w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
6 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram i cc operating conditions and maximum limits (notes: 1, 2, 3, 5, 6; notes can be found on page 9); v cc (min) v cc v cc (max) parameter/condition symbol speed 3.3v 5v units notes standby current: ttl i cc 1 all 1 2 ma (ras# = cas# = v ih ) standby current: cmos (non- ? s ? version only) i cc 2 all 500 500 a (ras# = cas# = other inputs = v cc - 0.2v) standby current: cmos ( ? s ? version only) i cc 2 all 150 150 a (ras# = cas# = other inputs = v cc - 0.2v) operating current: random read/write -5 180 190 average power supply current i cc 3 -6 170 180 ma 23 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: fast page mode -5 110 120 average power supply current i cc 4 -6 90 110 ma 23 (ras# = v il , cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only -5 180 190 average power supply current i cc 5 -6 170 180 ma (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr -5 180 180 average power supply current i cc 6 -6 170 180 ma 4, 7 (ras#, cas#, address cycling: t rc = t rc [min]) refresh current: extended ( ? s ? version only) average power supply current: cas# = 0.2v or cbr cycling; i cc 7 all 300 300 a 4, 7 ras# = t ras (min); we# = v cc - 0.2v; a0-a11, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open) refresh current: self ( ? s ? version only) average power supply current: cbr with ras# ? i cc 8 all 300 300 a 4, 7 t rass (min) and cas# held low; we# = v cc - 0.2v; a0-a11, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open) capacitance (note: 2; notes can be found on page 9); parameter symbol max units input capacitance: addresses c i 1 5pf input capacitance: ras#, casl#, cash#, we#, oe# c i 2 7pf input/output capacitance: dq c io 7pf
7 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); v cc (min) v cc v cc (max) ac characteristics -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column-address hold time (referenced to ras#) t ar 38 45 ns column-address setup time t asc 0 0 ns 27 row-address setup time t asr 0 0 ns column address to we# delay time t awd 42 49 ns 18 access time from cas t cac 15 15 ns 29 column-address hold time t cah 8 10 ns 27 cas# pulse width t cas 8 10,000 10 10,000 ns 32, 35 cas# low to ? don ? t care ? during self refresh t chd 15 15 ns cas# hold time (cbr refresh) t chr 8 10 ns 4, 28 last cas# going low to first cas# to return high t clch 10 10 ns 30 cas# to output in low-z t clz 0 0 ns 26, 29 cas# precharge time t cp 8 5 ns 30 access time from cas# precharge t cpa 28 35 ns 28 cas# to ras# precharge time t crp 5 5 ns 28 cas# hold time t csh 38 45 ns 28 cas# setup time (cbr refresh) t csr 5 5 ns 4, 27 cas# to we# delay time t cwd 28 35 ns 18, 27 write command to cas# lead time t cwl 8 10 ns 23, 29 data-in hold time t dh 8 10 ns 19, 29 data-in setup time t ds 0 0 ns 19, 29 output disable t od 0 12 0 15 ns 17, 26, 29 output enable t oe 12 15 ns 22 oe# hold time from we# during t oeh 8 10 ns 20 read-modify-write cycle output buffer turn-off delay t off 0 12 0 15 ns 11, 17, 23 oe# setup prior to ras# during hidden refresh cycle t ord 0 0 ns fast-page-mode read or write cycle time t pc 20 25 ns 31 fast-page-mode read-write cycle time t prwc 47 56 ns 31 access time from ras# t rac 50 60 ns ras# to column-address delay time t rad 9 12 ns 20 row-address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (fast page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width (self refresh) t rass 100 100 s random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 14, 27 read command hold time (referenced to cas) t rch 0 0 ns 16, 28 read command setup time t rcs 0 0 ns 27 refresh period (1,024 cycles) t ref 16 16 ms refresh period (1,024 cycles) ? s ? version t ref 128 128 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns ras# precharge time (self refresh) t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 16 ras# hold time t rsh 13 15 ns 36 read-write cycle time t rwc 116 140 ns
8 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); v cc (min) v cc v cc (max) ac characteristics -5 -6 parameter symbol min max min max units notes ras# to we# delay time t rwd 67 79 ns 18 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns 36 write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns 18, 27 write command pulse width t wp 5 5 ns we# hold time (cbr refresh) t wrh 8 10 ns we# setup time (cbr refresh) t wrp 8 10 ns
9 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = +3.3v or 5.0v; f = 1 mhz. 3. i cc is dependent on output loading. specified values are obtained with minimum cycle time and the output open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0c t a 70c) for commercial and (-20c t a 80c) for extended ?et? is ensured. 6. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#- only or cbr), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 5ns. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. if cas# = v ih , data output is high-z. 11. if cas# = v il , data output may contain data from the last valid read cycle. 12. measured with a load equivalent to two ttl gates, 100pf and v ol = 0.8v and v oh = 2v. 13. if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the q buffer, cas# must be pulsed high for t cp. 14. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 15. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac, and t cac must always be met. 16. either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 18. t wcs, t rwd, t awd, and t cwd are restrictive operating parameters in late write and read- modify-write cycles only. if t wcs t wcs (min), the cycle is an early write cycle and the data out-put will remain an open circuit through- out the entire cycle. if t rwd t rwd (min), t awd t awd (min) and t cwd t cwd (min), the cycle is a read write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of q (at access time and until cas# or oe# goes back to v ih ) is indeterminate. oe# held high and we# taken low after cas# goes low result in a late write (oe#-controlled) cycle. 19. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 20. during a read cycle, if oe# is low then taken high before cas# goes high, q goes open. if oe# is tied permanently low, late write and read-modify-write operations are not permissible and should not be attempted. 21. a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 22. all other inputs at 0.2v or v cc - 0.2v. 23. column address changed once each cycle. 24. late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously read data if cas# remains low and oe# is taken back low after t oeh is met. if cas# goes high prior to oe# going back low, the dqs will remain open. 25. the dqs open during read cycles once t od or t off occur. 26. the 3ns minimum is a parameter guaranteed by design. 27. the first casx edge to transition low. 28. the last casx edge to transition high. 29. output parameter (dqx) is referenced to corresponding cas# input; dq0-dq7 by casl# and dq8-dq15 by cash#. 30. last falling casx edge to first rising casx edge. 31. last rising casx edge to next cycle?s last rising casx edge.
10 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram notes (continued) 32. last rising casx edge to first falling casx edge. 33. first dqs controlled by the first casx to go low. 34. last dqs controlled by the last casx to go high. 35. each casx must meet minimum pulse width. 36. last casx to go low. 37. all dqs controlled, regardless casl# and cash#. 38. if oe# is tied permanently low, late write, or read-modify-write operations are not permissible and should not be attempted.
11 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v ioh iol v v ih il t od t oe oe# v v ih il column we# casl#/cash# t clch don?t care undefined timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 15 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 10 10 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns t oe 12 15 n s t off 0 12 0 15 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh 13 15 ns -5 -6 symbol min max min max units
12 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram don ? t care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh t clch we# casl#/cash# early write cycle timing parameters -5 -6 symbol min max min max units t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 10 10 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t rad 9 12 ns -5 -6 symbol min max min max units t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rp 30 40 n s t rsh 13 15 ns t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns
13 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh t clch we# casl#/cash# don ? t care undefined read-write cycle (late write and read-modify-write cycles) timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 15 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 10 10 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh 13 15 ns t rwc 116 140 ns t rwd 67 79 ns t rwl 13 15 n s t wp 5 5 ns -5 -6 symbol min max min max units
14 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram fast-page-mode read cycle valid data valid data valid data column column column row row don ? t care undefined t rcs t cah t asc t cp t rsh t cp t cp t cas, t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rch t rch t rcs t rrh t rch t off t cac t cpa t aa t clz t off t cac t cpa t aa t clz t off t cac t rac t aa t clz t oe t od t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t clch t cas, t clch t cas, t clch we# casl#/cash# timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 15 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 10 10 ns t clz 0 0 ns t cp 8 5 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns -5 -6 symbol min max min max units t oe 12 15 n s t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh 13 15 ns
15 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram fast-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t rsh t cp t cp t rcd t crp t pc t csh t rasp t rp v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t cas, t clch t cas, t clch t cas, t clch we# casl#/cash# don ? t care undefined timing parameters -5 -6 symbol min max min max units t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 10 10 ns t cp 8 5 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t pc 20 25 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rp 30 40 n s t rsh 13 15 ns t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns -5 -6 symbol min max min max units
16 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram fast-page-mode read-write cycle (late write and read-modify-write cycles) don ? t care undefined t od t oe t od t oe t od t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t rsh t cp t rp t rasp t cp t rcd t csh t pc note 1 t crp row column column column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t prwc oeh t cas, t clch t cas, t clch t cas, t clch we# casl#/cash# note: 1. t pc is for late write only. t ds 0 0 ns t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t pc 20 25 n s t prwc 47 56 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh 13 15 ns t rwd 67 79 ns t rwl 13 15 n s t wp 5 5 ns -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 15 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 10 10 ns t clz 0 0 ns t cp 8 5 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns
17 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram note: 1. t pc is for late write only. fast-page-mode read early write cycle (pseudo read-modify-write) row valid data valid data open t crp t rcd t cas t rsh t rasp t rp t pc t asc t cah t ar t asr t rad t rah t wcs t wp t rwl t rcs t dh t ds t cac t off v v ih il casl#/cash# v v ih il addr v v ih il ras# q v v oh ol we# v v ih il t csh column t cp t cp t asc t cah t cwl t wch t clz t aa rac don ? t care undefined t note 1 oe# v v ih il row column t cas timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 15 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 5 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns -5 -6 symbol min max min max units t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh 13 15 ns t rwl 13 15 n s t wch 8 10 ns t wcs 0 0 ns t wp 5 5 ns
18 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram t rp v v ih il ras# t ras open t chr t csr v v ih il casl#/cash# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# don ? t care undefined v v oh ol note 1 ras#-only refresh cycle (oe# and we# = don ? t care) row v v ih il v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open q v v oh ol t rpc casl#/cash# cbr refresh cycle (addresses and oe# = don ? t care) timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t chr 8 10 ns t cp 8 5 ns t crp 5 5 ns t csr 5 5 ns t rah 9 10 ns t ras 50 60 10,000 ns t rc 84 104 ns t rp 30 40 n s t rpc 5 5 ns t wrh 8 10 ns t wrp 8 10 ns -5 -6 symbol min max min max units note: 1. end of cbr refresh cycle.
19 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram hidden refresh cycle 1 (we# = high; oe# = low) don ? t care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rp t chr t ras dqx v v ioh iol v v ih il addr v v ih il v v ih il ras# t oe t od casl#/cash# v v ih il oe# t ord timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 15 15 n s t cah 8 10 ns t chr 8 10 ns t clz 0 0 ns t crp 5 5 ns t od 0 12 0 15 ns -5 -6 symbol min max min max units t oe 12 15 n s t off 0 12 0 15 ns t ord 0 0 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rp 30 40 n s t rsh 13 15 ns note: 1. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high.
20 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram self refresh cycle (addresses and oe# = don ? t care) v v ih il ras# t rass open v v ih il v v oh ol dq t rpc t chd t rps t rpc t rp t cp cas# we# v v ih il t wrh t wrp t wrh t wrp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note 1 t csr don ? t care undefined t cp note 2 ( ) ( ) ( ) ( ) note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed if ras#-only or burst cbr refresh is used. timing parameters -5 -6 symbol min max min max units t c h d 15 15 n s t clch 10 10 ns t cp 8 5 ns t csr 5 5 ns t rass 100 100 s -5 -6 symbol min max min max units t rp 30 40 n s t rpc 5 5 ns t rps 90 105 ns t wrh 8 10 ns t wrp 8 10 ns
21 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram 42-pin plastic soj (400 mil) .148 (3.76) .138 (3.51) 1.000 (25.40) 1.079 (27.41) 1.073 (27.25) seating plane .380 (9.65) .360 (9.14) .030 (0.76) min pin #1 index .050 (1.27) typ .445 (11.30) .435 (11.05) .405 (10.29) .399 (10.13) .095 (2.40) .080 (2.02) .020 (0.51) .015 (0.38) .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
22 1 meg x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d51_5v_b.p65 ? rev. b; pub 3/01 ?2001, micron technology, inc. 1 meg x 16 fpm dram 44/50-pin plastic tsop (400 mil) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark and the micron logo and m logo are trademarks of micron technology, inc. see detail a .024 (0.60) .016 (0.40) .008 (0.20) .002 (0.05) detail a .010 (0.25) .032 (0.80) typ .007 (0.18) .005 (0.13) .047 (1.20) max .004 (0.10) .031 (0.80) typ 1 50 25 .018 (0.45) .012 (0.30) .828 (21.04) .822 (20.88) .467 (11.86) .459 (11.66) .402 (10.21) .398 (10.11) pin #1 index seating plane .029 (0.75) typ

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